E-ISSN 2705-3954 | ISSN 0794-4756
 

Original Research 
NJE. 2024; 31(1): 125-137


SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN

KINGSLEY ESEMWENRE OSAKUE-HENRY, ALI ZEKI.


Abstract
As a new technique for reducing leakage power in deep sub-micron technology node, Sleepy-Pass Gate Keeper technique is proposed in this paper, which is a hybrid of Sleepy-Pass Gate and Sleepy Keeper techniques. Performance verifications were performed via LTspice simulations of 3-input NAND and 3-input NOR gates designed to implement the proposed technique. Performance comparisons with equivalent NOR3 and NAND3 gates based on Sleepy Keeper and Sleepy-Pass Gate techniques, revealed that the proposed technique outperforms the counterparts in terms of average leakage power consumption. Average leakage power of NAND3 and NOR3 gates using the new technique are 32% and 40% of those of Sleepy Keeper NAND3 and NOR3, and 57% and 20% of those of Sleepy-Pass Gate NAND3 and NOR3, respectively.

Key words: Leakage power, Propagation delay, Sub-threshold current, Power-delay-product.


 
ARTICLE TOOLS
Abstract
PDF Fulltext
How to cite this articleHow to cite this article
Citation Tools
Related Records
 Articles by KINGSLEY ESEMWENRE OSAKUE-HENRY
Articles by ALI ZEKI
on Google
on Google Scholar

How to Cite this Article
Pubmed Style

OSAKUE-HENRY KE, ZEKI A, . SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN. NJE. 2024; 31(1): 125-137.


Web Style

OSAKUE-HENRY KE, ZEKI A, . SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN. https://www.njeabu.com.ng/?mno=158978 [Access: April 11, 2024].


AMA (American Medical Association) Style

OSAKUE-HENRY KE, ZEKI A, . SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN. NJE. 2024; 31(1): 125-137.



Vancouver/ICMJE Style

OSAKUE-HENRY KE, ZEKI A, . SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN. NJE. (2024), [cited April 11, 2024]; 31(1): 125-137.



Harvard Style

OSAKUE-HENRY, K. E., ZEKI, A. & (2024) SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN. NJE, 31 (1), 125-137.



Turabian Style

OSAKUE-HENRY, KINGSLEY ESEMWENRE, ALI ZEKI, and . 2024. SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN. Nigerian Journal of Engineering, 31 (1), 125-137.



Chicago Style

OSAKUE-HENRY, KINGSLEY ESEMWENRE, ALI ZEKI, and . "SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN." Nigerian Journal of Engineering 31 (2024), 125-137.



MLA (The Modern Language Association) Style

OSAKUE-HENRY, KINGSLEY ESEMWENRE, ALI ZEKI, and . "SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN." Nigerian Journal of Engineering 31.1 (2024), 125-137. Print.



APA (American Psychological Association) Style

OSAKUE-HENRY, K. E., ZEKI, A. & (2024) SLEEPY-PASS GATE KEEPER: A NOVEL TECHNIQUE FOR LEAKAGE POWER REDUCTION IN CMOS VLSI DESIGN. Nigerian Journal of Engineering, 31 (1), 125-137.